This invention relates to bubble memory systems organized on a word or byte basis. Herein a byte is defined as eight bits. A word can be any arbitrary number of bits. In particular, this invention relates to a system which allows defective, individual bubble memory chips to be used in a system wherein a logic system combined with a Programmable Read Only Memory (PROM) and an extra bubble memory chip provide a fault tolerance capability such that the output of the bubble memory system provides correct words or bytes.
In conventional manufacturing processes for bubble memory chips, a certain number of chips will be defective. Normal manufacturing control requires a trade-off between manufacturing 100 percent perfect devices and testing after the manufacturing process to find defective but useable units. Various designs in the prior art exist to increase the yield of useable chips by designing bubble memory chips in such a way that some number of faults or defects may exist and yet have the chip useable in the particular bubble memory system. Many such fault tolerant designs exist employing both external logic and memory as well as various modifications of a standard chip design or combinations of both.
The present invention involves a system wherein the testing process for the bubble memory chips will produce a map or list of the defective major loop address locations for each chip and wherein the chips can be sorted so that the chips comprising a byte or word of a memory may be selected so that no two or more chips have defective bits in the same major loop address positions. In the present invention each bubble memory chip need only have the number of major loop bit locations as required to maintain the nominal memory size.
U.S. Pat. No. 3,909,810 shows a scheme wherein extra minor loops are included in each chip in a bubble memory system and an external memory source is used together with logic devices to identify minor loops which are to be ignored in favor of usable minor loops. Thus, all of the fault tolerant ability of the system shown in this patent is based on external logic devices combined with the necessity of having bubble memory chips containing an excess number of minor loops.
In another form of fault tolerant capability, U.S. Pat. No. 3,792,450 shows the use of a major loop, minor loop memory system having additional minor loops which are used for the purpose of containing a flaw table to identify the minor loop locations which are defective. This system provides for additional complexity to the individual bubble memory chips in that additional connections and read gates are required on the chip to allow for independent reading of the minor loop flaw tables. Thus, further care in design and construction of individual bubble memory chips is required to ensure that proper synchronization is maintained between the redundant loops and the remainder of the memory so that the correct correspondence is maintained and identify between indications of faulty loops and the actual loops which are defective.
The present invention has many advantages over the type of fault tolerant system shown in U.S. Pat. No. 3,909,810 in that a bubble memory device is not required to serve as a flag chip containing only information about defective byte locations. The present invention uses only bubble memory chips for storage of data. The defect map memory device or flaw table, as it is sometimes called, of the present invention is contained in a PROM memory. Similarly, the present invention has advantages over systems involving extra or redundant minor loops in bubble memory devices because such systems require some type of mechanism for compacting data or buffering data in order to compensate for interruptions in the regular flow of data from a bubble memory when a bit location is skipped as the device is read in a serial fashion.